Senior ASIC Place-and-Route Product Engineer

Cadence Design Systems; San Jose (CA); Hybrid; USD 179,000 - 332,000; Full time

Benefits offered by this job

Bonus & Equity

Medical / Dental / Vision

Paid time off

Job summary

Cadence Design Systems in California is seeking a Product Engineer to drive development of advanced chip design software tools. You will provide place-and-route expertise to Cadence customers and internal teams and collaborate with R&D, application engineering and product marketing.

The role requires a BS in Electrical Engineering with at least seven years in digital implementation, strong VLSI, timing analysis, clock tree synthesis and signoff at 7nm and below, plus experience with EDA tools

Qualifications

• BS in Electrical Engineering with at least seven years in digital implementation as either a design or product engineer.
• Solid understanding of VLSI physical design and timing analysis, including clock tree synthesis, routing optimization, and silicon signoff challenges.
• Experience with industry-standard EDA tools for synthesis, physical design, and signoff at 7nm and below.
• Proficiency in scripting languages or AI tools for productivity enhancement.
• Strong verbal and written communication skills.

Responsibilities

• Supporting Cadence’s digital products.
• Tracking and resolving customer issues alongside R&D and release teams.
• Conducting design benchmarks.
• Developing innovative flows and methodologies tailored to customer needs.

Skills

Place-and-route

Timing closure

PPA optimization

VLSI design

Clock tree synthesis

Routing optimization

Silicon signoff

Scripting

Education

BS in Electrical Engineering

Tools

EDA tools (7nm+)

Job description

Cadence Design Systems in California is seeking a Product Engineer to drive development of advanced chip design software tools. You will provide place-and-route expertise to Cadence customers and internal teams and collaborate with R&D, application engineering and product marketing.

The role requires a BS in Electrical Engineering with at least seven years in digital implementation, strong VLSI, timing analysis, clock tree synthesis and signoff at 7nm and below, plus experience with EDA tools