Senior Product Engineer - ASIC Timing & Signoff

Cadence Design Systems; Austin (TX); On-site; USD 100,000 - 140,000; Full time

Job summary

Cadence is seeking a Product Engineer for the Digital and Signoff Group (DSG) to provide expert place-and-route know-how for ASIC flows from RTL to GDSII. You will help customers and R&D debug issues, run benchmarks, and contribute to solution development.

The ideal candidate has 5+ years in digital implementation and hands-on experience with timing closure, PPA optimization, and EDA tools across 16nm and below nodes. Strong communication and automation scripting are essential.

Qualifications

• MS in EE with 5+ years of Digital Implementation experience, either as a design engineer or as a product engineer.
• BS in EE with 8+ years of Digital Implementation experience, either as a design engineer or as a product engineer.
• Familiarity with RTL synthesis, placement optimization, clock tree synthesis, routing optimization and silicon signoff.

Responsibilities

• Support Cadence products in the Digital and Signoff team.
• Track and debug customer issues and work with R&D and release team on issue resolution.
• Run design benchmarks and develop flows and solutions.

Skills

VLSI physical design

Timing analysis

RTL synthesis

Placement optimization

Clock tree synthesis

Routing optimization

Silicon signoff

Perl scripting

Tcl scripting

Shell scripting

Communication

Problem solving

Automation

Education

MS in EE

BS in EE

Tools

Industry standard EDA tools

Job description

Cadence is seeking a Product Engineer for the Digital and Signoff Group (DSG) to provide expert place-and-route know-how for ASIC flows from RTL to GDSII. You will help customers and R&D debug issues, run benchmarks, and contribute to solution development.

The ideal candidate has 5+ years in digital implementation and hands-on experience with timing closure, PPA optimization, and EDA tools across 16nm and below nodes. Strong communication and automation scripting are essential.