Principal Product Engineer, Digital & Signoff

Cadence; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Cadence seeks a Product Engineer in the Digital and Signoff Group to provide expert place-and-route support for ASIC design flows. You will work with R&D and customer teams to influence tool development and resolve advanced RTL-to-GDSII issues.

The role emphasizes strong analysis, communication, and problem-solving skills and requires 5+ years in Digital Implementation (MS) or 8+ years (BS) in relevant areas, with hands-on timing closure and PPA optimization at 16nm and below.

Qualifications

• MS in EE with 5+ years of Digital Implementation experience.
• BS in EE with 8+ years of Digital Implementation experience.
• Strong understanding of VLSI physical design and timing analysis.
• Experience with industry standard EDA tools at 16nm and below.

Responsibilities

• Support Cadence products in the Digital and Signoff team.
• Track and debug customer issues and work with R&D and release teams on issue resolution.
• Run design benchmarks and develop flows and solutions.

Skills

Digital Implementation

RTL to GDSII flow

Timing closure

PPA optimization

VLSI physical design

RTL synthesis

Placement optimization

Clock tree synthesis

Routing optimization

Silicon signoff

Hierarchical design

Low power design

Perl

Tcl

Shell scripting

Communication

Problem solving

Education

Master's in EE

Bachelor's in EE

Tools

EDA tools

Job description

Cadence seeks a Product Engineer in the Digital and Signoff Group to provide expert place-and-route support for ASIC design flows. You will work with R&D and customer teams to influence tool development and resolve advanced RTL-to-GDSII issues.

The role emphasizes strong analysis, communication, and problem-solving skills and requires 5+ years in Digital Implementation (MS) or 8+ years (BS) in relevant areas, with hands-on timing closure and PPA optimization at 16nm and below.