Director of ASIC Design & Front-End Implementation

HITEC; Roseville (CA); On-site; USD 230,000 - 300,000; Full time

Job summary

Hewlett Packard Enterprise is seeking an accomplished Director-level ASIC Design Leader to drive RTL implementation and tapeout readiness for next-generation networking ASICs. You will lead architecture-to-production efforts, align with architecture, verification, physical design, software, and product teams, and set standards for design quality and delivery.

In this role, you will shape technology strategy, manage multiple ASIC programs, and mentor senior engineers to build a high-performing,

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of ASIC development experience, including 8+ years leading engineering teams.
• Expertise in RTL design, Verilog/SystemVerilog, microarchitecture development, synthesis, CDC, linting, timing closure, and ASIC implementation flows.
• Proven success delivering complex ASICs from concept through production.

Responsibilities

• Lead RTL design and microarchitecture teams delivering networking ASICs.
• Drive design execution from architecture through RTL completion, ensuring PPA targets are met.
• Establish design methodologies and engineering best practices.
• Collaborate across Architecture, Verification, Physical Design, Software, Emulation, and Post-Silicon teams.
• Represent the design organization in roadmap reviews and executive discussions.

Skills

RTL design

Verilog/SystemVerilog

microarchitecture

synthesis

timing closure

EDA/ASIC flows

leadership

Education

BS/MS in Electrical Engineering

Job description

Hewlett Packard Enterprise is seeking an accomplished Director-level ASIC Design Leader to drive RTL implementation and tapeout readiness for next-generation networking ASICs. You will lead architecture-to-production efforts, align with architecture, verification, physical design, software, and product teams, and set standards for design quality and delivery.

In this role, you will shape technology strategy, manage multiple ASIC programs, and mentor senior engineers to build a high-performing,