Director, ASIC Design & Front-End Implementation

Hewlett Packard Enterprise; Roseville (CA); On-site; USD 210,000 - 260,000; Full time

Job summary

Hewlett Packard Enterprise in the United States is seeking a Director-level leader to head the ASIC Design and Front-End Implementation organization. You will drive RTL design, microarchitecture, and tapeout readiness for next-generation networking ASICs powering HPE Networking products.

You will collaborate across Architecture, Verification, Physical Design, Software, and Product Management, lead engineering managers and teams, and shape technology strategy, roadmaps, and execution across

Qualifications

• 15+ years of ASIC development experience.
• 8+ years leading engineering teams and managers.
• Expertise in RTL design, Verilog/SystemVerilog, microarchitecture development, synthesis, CDC, linting, timing closure, and ASIC implementation flows.
• Proven success delivering complex ASICs from concept through production.
• Strong cross-functional leadership, communication, and program execution skills.

Responsibilities

• Lead RTL design and microarchitecture teams for complex networking ASICs.
• Drive design execution from architecture through RTL completion to meet performance, power, area, quality, cost and schedule targets.
• Establish design methodologies, coding standards, and engineering best practices.
• Review and approve architectural and implementation trade-offs.
• Partner with Physical Design for floorplanning, timing closure, power optimization, DFT and tapeout readiness.
• Ensure RTL designs are optimized for manufacturability, scalability, and production readiness.
• Foster cross-functional collaboration across Architecture, Verification, Physical Design, SDK/Software, and Product Management.
• Contribute to technology strategy and product roadmaps; represent design in roadmap reviews and executive discussions.
• Lead multiple ASIC programs, managing schedules, dependencies and risks; mentor engineering managers and engineers.

Skills

RTL design

Verilog/SystemVerilog

microarchitecture development

synthesis

CDC

linting

timing closure

ASIC implementation flows

cross-functional leadership

program execution

Education

BS/MS in Electrical Engineering / Computer Engineering

Job description

Hewlett Packard Enterprise in the United States is seeking a Director-level leader to head the ASIC Design and Front-End Implementation organization. You will drive RTL design, microarchitecture, and tapeout readiness for next-generation networking ASICs powering HPE Networking products.

You will collaborate across Architecture, Verification, Physical Design, Software, and Product Management, lead engineering managers and teams, and shape technology strategy, roadmaps, and execution across