Senior ASIC Design Engineer — ML Inference Acceleration

Amazon; Austin (TX); On-site; USD 110,000 - 160,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

RSUs

Job summary

Amazon is seeking an ASIC Design Engineer in Austin, TX to design and optimize hardware for AWS ML servers. You will develop RTL in SystemVerilog, run timing and lint checks, and collaborate with cross-functional teams to balance performance, area, and power while ensuring design quality.

The ideal candidate has a strong ASIC design background, SystemVerilog expertise, and a proven ability to debug complex architectures. A Bachelor’s in EE is required; advanced degrees are preferred.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• Experience identifying bugs in architecture, algorithms, functionality, and performance with strong debugging skills.
• Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing.

Responsibilities

• Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets.
• Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements.
• Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints.
• Execute lint and clock domain crossing quality checks to ensure design integrity.
• Collaborate closely with cross-functional teams including architects, verification specialists, and synthesis, timing, and back-end experts.

Skills

ASIC design

SystemVerilog

Debugging skills

Analytical skills

Power-efficient design

Education

Bachelor's degree in Electrical Engineering or related field

Master's or Ph.D. in Electrical Engineering or related field

Tools

Python

Perl

Job description

Amazon is seeking an ASIC Design Engineer in Austin, TX to design and optimize hardware for AWS ML servers. You will develop RTL in SystemVerilog, run timing and lint checks, and collaborate with cross-functional teams to balance performance, area, and power while ensuring design quality.

The ideal candidate has a strong ASIC design background, SystemVerilog expertise, and a proven ability to debug complex architectures. A Bachelor’s in EE is required; advanced degrees are preferred.