Senior ASIC Design Engineer for Cloud ML Acceleration

Amazon Web Services (AWS); Cupertino (CA); On-site; USD 183,000 - 248,000; Full time

Job summary

Amazon Web Services (AWS) is seeking an ASIC Design Engineer to help advance SOC-level RTL design and VLSI engineering for high-performance cloud hardware. The role emphasizes delivering efficient, scalable RTL, leveraging SystemVerilog, and collaborating with cross-functional teams in a fast-paced data center environment.

The candidate should have 5+ years in RTL design for SOC and VLSI, with expertise in code quality tools like Spyglass, LINT, and CDC, plus strong scripting for automation.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• 5+ years in RTL design for SOC.
• 5+ years of VLSI engineering.
• 5+ years with code quality tools including Spyglass, LINT, or CDC.

Responsibilities

• Integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/DFT signal routing.
• As a key member of the ASIC design team, you will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
• Analyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirements.
• Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints.
• Perform lint and clock domain crossing quality checks on the design.
• Work with architects, other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing and back-end teams to accomplish your tasks.

Skills

RTL design for SOC

VLSI engineering

Python scripting

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree or Ph.D. in Electrical Engineering or related field

Tools

Spyglass

LINT

CDC

SystemVerilog RTL

Job description

Amazon Web Services (AWS) is seeking an ASIC Design Engineer to help advance SOC-level RTL design and VLSI engineering for high-performance cloud hardware. The role emphasizes delivering efficient, scalable RTL, leveraging SystemVerilog, and collaborating with cross-functional teams in a fast-paced data center environment.

The candidate should have 5+ years in RTL design for SOC and VLSI, with expertise in code quality tools like Spyglass, LINT, and CDC, plus strong scripting for automation.