Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs (AWS)

Amazon; Cupertino (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Annapurna Labs, part of Amazon, is seeking a Sr. ASIC Design Engineer to drive RTL design and optimization for cloud-scale ML acceleration.

You will implement high-performance, power-aware SoC RTL, integrate subsystems, analyze trade-offs, and collaborate across architects, verification, and back-end teams to deliver scalable hardware for AWS ML servers.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years in RTL design for SOC.
• 5+ years in VLSI engineering.
• 5+ years with code quality tools including Spyglass, LINT, or CDC.

Responsibilities

• Implement high-performance RTL to meet design targets.
• Integrate subsystems into top-level SOC with proper routing.
• Analyze design trade-offs for features, power, and area.
• Develop micro-architecture and SystemVerilog RTL; deliver clean designs.
• Perform lint and clock domain crossing checks.
• Collaborate with architects, verification, and back-end teams.

Skills

RTL design

SystemVerilog

Python scripting

Data path design

Communication skills

Education

Bachelor's degree in Electrical Engineering

Master's degree in EE/CE

Tools

SpyGlass

LINT

CDC

Job description

Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs

Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server.

Key job responsibilities

• Implement and deliver high performance, area- and power‑efficient RTL to achieve design targets and specifications.
• Integrate multiple subsystems into top‑level SOC, ensuring correct clock/reset/functional/DFT signal routing.
• Analyze design, microarchitecture, or architecture to make trade‑offs based on features, power, performance or area requirements.
• Develop micro‑architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints.
• Perform lint and clock domain crossing quality checks on the design.
• Work with architects, other designers, verification teams, pre‑ and post‑silicon validation teams, synthesis, timing and back‑end teams to accomplish tasks.

Preferred Qualifications

• Experience in RTL coding and debug, as well as performance, power, area analysis and trade‑offs.
• Master's degree in electrical engineering, computer engineering, or equivalent.
• 5+ years of practical semiconductor design work including full‑chip and subsystem integration experience.
• Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints.
• Experience with automation and scripting languages such as Python.
• Familiarity with data path design, interconnects, AXI protocol.
• Good analytical, problem solving, and communication skills.

Basic Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• 5+ years in RTL design for SOC.
• 5+ years in VLSI engineering.
• 5+ years with code quality tools including Spyglass, LINT, or CDC.

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.