Cloud-Scale ML Acceleration ASIC Design Engineer

Amazon Web Services (AWS); Cupertino (CA); On-site; USD 157,000 - 213,000; Full time

Job summary

Amazon Web Services (AWS) seeks an ASIC Design Engineer to design, optimize, and implement high-performance RTL blocks for data-center accelerators. You will work on SystemVerilog RTL, timing and synthesis, and collaborate with architects, verification teams, and back-end experts in a fast-paced, inclusive environment.

The role is based in Cupertino, CA with potential relocation considerations. The ideal candidate has strong debugging skills, experience with verification at multiple levels, and

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• Experience identifying bugs in architecture, algorithms, functionality, and performance with strong debugging skills.
• Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing.

Responsibilities

• Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets.
• Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements.
• Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints.
• Execute lint and clock domain crossing quality checks to ensure design integrity.
• Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts.

Skills

Bug identification

Debugging

SystemVerilog knowledge

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Python

Perl

Scripting for automation

SystemVerilog

Job description

Amazon Web Services (AWS) seeks an ASIC Design Engineer to design, optimize, and implement high-performance RTL blocks for data-center accelerators. You will work on SystemVerilog RTL, timing and synthesis, and collaborate with architects, verification teams, and back-end experts in a fast-paced, inclusive environment.

The role is based in Cupertino, CA with potential relocation considerations. The ideal candidate has strong debugging skills, experience with verification at multiple levels, and