Senior ASIC Design Engineer II - High-Perf SoCs (RSUs)

Amazon; Cupertino (CA); On-site; USD 157,000 - 213,000; Full time

Benefits offered by this job

Health insurance

RSUs

Paid time off

Parental leave

Job summary

Amazon in Cupertino, CA is seeking an ASIC Design Engineer to design and optimize high-performance RTL hardware for AWS machine-learning datacenters. You will develop SystemVerilog RTL and microarchitectures, balancing power, area, and performance while coordinating with architects, verification, and back-end teams.

The role emphasizes a strong ASIC design background, SystemVerilog proficiency, and problem-solving skills, with a focus on scalable, energy-efficient solutions for data-center

Qualifications

• Bachelor's degree or equivalent required.
• 3+ years of non-internship design or architecture experience on new or existing systems.

Responsibilities

• Develop and implement high-performance RTL designs meeting project specs.
• Analyze designs, microarchitectures, and architectures to optimize features, power, performance and area trade-offs.
• Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with constraints.
• Execute lint and clock-domain crossing quality checks to ensure design integrity.
• Collaborate with cross-functional teams including architects, verification, and back-end experts.

Skills

SystemVerilog

ASIC design

Analytical skills

Problem-solving

Education

Master's degree in computer science

Job description

Amazon in Cupertino, CA is seeking an ASIC Design Engineer to design and optimize high-performance RTL hardware for AWS machine-learning datacenters. You will develop SystemVerilog RTL and microarchitectures, balancing power, area, and performance while coordinating with architects, verification, and back-end teams.

The role emphasizes a strong ASIC design background, SystemVerilog proficiency, and problem-solving skills, with a focus on scalable, energy-efficient solutions for data-center