Senior ASIC Design Engineer - Memory Subsystem

NVIDIA Corporation; Santa Clara (CA); Presencial; USD 136 000 - 265 000; Tempo integral

Resumo da oferta

NVIDIA Corporation in Santa Clara, CA is seeking a Senior ASIC Design Engineer to join our Memory Subsystem Design team. You will contribute to RTL design, synthesis and timing analysis, collaborating across architects, verification, and physical design to deliver high-performance interconnects.

Required: BS or MS in EE/CE, 5+ years of experience, Verilog/VHDL proficiency; CHI/CXL/PCI-E knowledge is a plus.

Qualificações

• BS or MS in Electrical Engineering or Computer Engineer or related degree
• 5+ years of experience
• Experience with high-speed coherent interconnects, protocol bridges, hardware-managed coherency and system level caches is a plus
• Experience with multiple clock domains and asynchronous interfaces is a plus
• Knowledge of industry specifications like CHI/CXL/PCI-E is a plus
• Strong proficiency of Verilog or VHDL
• Scripting language like PERL

Responsabilidades

• RTL design, synthesis and timing analysis responsibilities as part of the Memory Subsystem team
• Collaborate with architects, verification, formal verification and physical design teams to deliver high-performance interconnects

Conhecimentos

Verilog/VHDL

High-speed interconnects

Clock domains

CHI/CXL/PCI-E knowledge

Perl scripting

Collaboration with architects/verify/•

Formação académica

BS/MS in Electrical or Computer Engineering

Descrição da oferta de emprego

NVIDIA Corporation in Santa Clara, CA is seeking a Senior ASIC Design Engineer to join our Memory Subsystem Design team. You will contribute to RTL design, synthesis and timing analysis, collaborating across architects, verification, and physical design to deliver high-performance interconnects.

Required: BS or MS in EE/CE, 5+ years of experience, Verilog/VHDL proficiency; CHI/CXL/PCI-E knowledge is a plus.