Senior ASIC Design Engineer: Lead RTL for High-Perf GPUs

NVIDIA; Santa Clara (CA); On-site; USD 168,000 - 264,500; Full time

Benefits offered by this job

Equity

Comprehensive benefits

Job summary

NVIDIA is looking for a Senior ASIC Design Engineer based in Santa Clara, California. You will be a key member of the GPU Design team, implementing high-performance, area-efficient RTL for leading SoCs and GPUs.

The ideal candidate has a Bachelor's degree in Electrical Engineering or similar, with 8+ years of experience in micro-architecture and RTL development. Strong C/C++ and Verilog skills are a plus. This position offers a competitive salary, equity, and benefits.

Qualifications

• 8+ years of meaningful work experience.
• Great understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
• Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic.

Responsibilities

• Implement, document and deliver high performance, area and power efficient RTL.
• Analyze architectural trade‑offs based on features and performance requirements.
• Collaborate with architects, designers, and verification teams.

Skills

Micro-architecture and RTL development (Verilog)

Strong C/C++, Python or Perl skills

Debugging and analytical skills

Education

Bachelor's Degree in Electrical Engineering, Computer Engineering or Computer Science

Job description

NVIDIA is looking for a Senior ASIC Design Engineer based in Santa Clara, California. You will be a key member of the GPU Design team, implementing high-performance, area-efficient RTL for leading SoCs and GPUs.

The ideal candidate has a Bachelor's degree in Electrical Engineering or similar, with 8+ years of experience in micro-architecture and RTL development. Strong C/C++ and Verilog skills are a plus. This position offers a competitive salary, equity, and benefits.