Senior Logic Design Engineer - Cache Coherent Interconnects

NVIDIA Corporation; Santa Clara (CA); Híbrido; USD 136 000 - 265 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Hybrid work model

Resumo da oferta

NVIDIA Corporation is seeking a Senior Logic Design Engineer to design CPU on-chip/off-chip interconnects, MP coherency, and system caches. You will craft RTL, assist timing closure, and collaborate with verification and implementation teams to meet aggressive performance and power targets.

Requires a Master's degree in a related field and 5+ years in high-performance semiconductor design. Hybrid work arrangement with opportunities across a global team are offered.

Qualificações

• Master's degree is required or equivalent experience.
• 5+ years of experience in processor or related high performance semiconductor designs.
• Verilog expertise and ASIC design flow knowledge (RTL, verification, synthesis, timing).
• Strong communication and interpersonal skills; mentoring junior engineers is a plus.
• Background in computer architecture, cache coherency or high-speed interconnects is helpful.

Responsabilidades

• Write readable, high-performance, low-power RTL for a CPU unit.
• Perform synthesis and timing closure; contribute to design documentation.
• Collaborate with verification team to ensure correctness of your unit.
• Work with implementation to meet timing, area, performance and power goals.
• Assist with timing closure of super units.

Conhecimentos

Mentoring junior engineers

Strong communication

Collaborative mindset

Timing closure experience

Formação académica

Master's degree in Electrical Engineering, Computer Engineering or Computer Science

Ferramentas

Verilog

DFT

Timing analysis

Descrição da oferta de emprego

NVIDIA Corporation is seeking a Senior Logic Design Engineer to design CPU on-chip/off-chip interconnects, MP coherency, and system caches. You will craft RTL, assist timing closure, and collaborate with verification and implementation teams to meet aggressive performance and power targets.

Requires a Master's degree in a related field and 5+ years in high-performance semiconductor design. Hybrid work arrangement with opportunities across a global team are offered.