Senior ASIC Design Engineer — Memory Subsystem (Equity)

NVIDIA

Santa Clara (CA)

On-site

USD 136,000 - 265,000

Full time

14 days+

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Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior ASIC Design Engineer to join our Memory Subsystem Team in Santa Clara. You will collaborate with architects, verification, formal verification and physical design to deliver a world-class memory subsystem solution.

You will own micro-architecture and design, including RTL, synthesis and timing analysis, using innovative CAD tools and the latest process technologies. NVIDIA offers base salaries for Level 3 and Level 4, plus equity and benefits; applications open until

Qualifications

BS or MS in Electrical Engineering or Computer Engineering (or equivalent).
5+ years of experience.
Experience with high-speed coherent interconnects, protocol bridges and system-level caches is a plus.
Experience with multiple clock domains and asynchronous interfaces is a plus.
Knowledge of CHI/CXL/PCI-E is a plus.
Strong proficiency of Verilog or VHDL.
Scripting language like PERL.

Responsibilities

Collaborate with architects, verification, formal verification and physical design teams to deliver a world-class memory subsystem solution.
Responsible for micro-architecture and design including RTL design, synthesis and timing analysis using CAD tools and latest process technologies.