Senior Memory Systems Engineer - DDR/HBM Architect (Equity)

NVIDIA; Santa Clara (CA); On-site; USD 184,000 - 357,000; Full time

Job summary

NVIDIA is seeking a Senior Memory System Engineer to join the ASIC Memory Subsystem team in California. You will collaborate with memory controller, PHY, firmware, and SI/PI teams to design high‑speed, low‑power memory solutions for Tegra SOCs and CPUs.

You will analyze DDR/LPDDR/HBM technologies, define memory modules and layouts, and work with DRAM suppliers to validate memory designs. Proficiency in Python/C++ and a deep understanding of memory subsystems are required.

Qualifications

• Bachelor's or master's degree in Electrical or Computer Engineering or related field.
• 10+ years of proven experience in DRAM design, module design, or memory subsystem design.
• Strong memory design fundamentals, ECC algorithms, SI/PI knowledge in DDR/LPDDR/HBM.
• Solid understanding of memory-subsystem interactions with cache, memory controller and PHY.
• Experience with memory bring-up, validation, and failure analysis.
• Proficiency in Python and C/C++ for development and workload analysis.

Responsibilities

• Analyze future DDR/LPDDR/HBM technologies for optimum performance and reliability.
• Collaborate with ASIC Architects, Designers, Software and Firmware teams on memory requirements.
• Define memory module, package, and PCB layouts for system workloads.
• Debug and bring up memory evaluation, validation and failure issues.
• Collaborate with DRAM suppliers to develop memory technology.

Skills

Memory design

ECC algorithms

SI/PI

Python

C/C++

Memory subsystem

Interpersonal skills

Education

Bachelor's/Master's in EE/CE

Job description

NVIDIA is seeking a Senior Memory System Engineer to join the ASIC Memory Subsystem team in California. You will collaborate with memory controller, PHY, firmware, and SI/PI teams to design high‑speed, low‑power memory solutions for Tegra SOCs and CPUs.

You will analyze DDR/LPDDR/HBM technologies, define memory modules and layouts, and work with DRAM suppliers to validate memory designs. Proficiency in Python/C++ and a deep understanding of memory subsystems are required.