Senior Memory Systems Engineer — Hybrid & Equity

NVIDIA Corporation; Santa Clara (CA); On-site; USD 184,000 - 357,000; Full time

Benefits offered by this job

Equity

Competitive benefits

Job summary

NVIDIA Corporation is seeking a Senior Memory System Engineer to join the ASIC Memory Subsystem team. You will work across memory controllers, PHY, firmware, and system architects to design high-speed, low-power memory solutions for Tegra SoCs.

You will analyze DDR/LPDDR/HBM technologies, define memory module layouts, and collaborate with memory suppliers to push technology forward. Strong background in DRAM design and memory subsystem interaction is required.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10 years of proven DRAM design or memory subsystem experience.
• Deep understanding of memory design, ECC, SI/PI in DDR, LPDDR, and HBM.
• Experience with memory workload analysis and scripting (Python).

Responsibilities

• Analyze future DDR/LPDDR/HBM technologies to determine optimum performance, power, function and RAS in memory for Next generation SOC and Systems.
• Collaborate with ASIC Architects, Designers, Software and Firmware SW/FW teams to drive memory technology and associated requirements for memory controllers.
• Define Memory module, Package, and PCB layouts appropriate to the system workloads
• Debug and bring up memory evaluation / validation and failure issues on memory technology.
• Collaborate with DRAM suppliers and industry partners on to develop memory and memory related component technology.

Skills

Python

C/C++

Memory systems

DRAM design

ECC

Education

Bachelor's or Master's in Electrical Engineering or Computer Engineering

Tools

Memory simulators

Job description

NVIDIA Corporation is seeking a Senior Memory System Engineer to join the ASIC Memory Subsystem team. You will work across memory controllers, PHY, firmware, and system architects to design high-speed, low-power memory solutions for Tegra SoCs.

You will analyze DDR/LPDDR/HBM technologies, define memory module layouts, and collaborate with memory suppliers to push technology forward. Strong background in DRAM design and memory subsystem interaction is required.