ASIC Clocking Engineer — PPA, RTL & Silicon, Equity

NVIDIA Corporation; Santa Clara (CA); On-site; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation is seeking an ASIC Clocking Engineer to architect the clock domain for GPU/CPU, balancing functional, physical and testing requirements. You will collaborate across design, floorplanning, and lab teams to deliver robust clocking solutions and improve PPA across DFx, timing, and power.

You will work with Verilog RTL, verification and scripting to implement scalable clocking topologies, contributing to silicon bringup and end-to-end ASIC cycles.

Qualifications

• BS in Electrical Engineering or equivalent; MS preferred.
• 2+ years of relevant ASIC/clocking experience.
• Understanding of logic optimization and PPA trade-offs.
• Experience in RTL design (Verilog), verification and logic synthesis.
• Strong Python or scripting language skills.
• Knowledge of sub-micron silicon issues (noise, cross-talk, OCV) a plus.
• Experience with on-chip clocking networks is a bonus.

Responsibilities

• Architect the clock domain to satisfy functional, physical and testing design requirements.
• Engage with multiple teams to design GPU/CPU clocks meeting constraints.
• Improve Power, Performance and Area (PPA) across DFx, Physical Implementation, and timing.
• Collaborate with Physical, timing, and DFT teams to deliver clock RTL to verification.
• Participate in end-to-end ASIC cycle from micro-arch to silicon bringup.

Skills

RTL design

Python scripting

PPA trade-offs

Interpersonal collaboration

Verilog

Clocking networks knowledge

Silicon timing issues awareness

Education

BS in Electrical Engineering or equivalent

Job description

NVIDIA Corporation is seeking an ASIC Clocking Engineer to architect the clock domain for GPU/CPU, balancing functional, physical and testing requirements. You will collaborate across design, floorplanning, and lab teams to deliver robust clocking solutions and improve PPA across DFx, timing, and power.

You will work with Verilog RTL, verification and scripting to implement scalable clocking topologies, contributing to silicon bringup and end-to-end ASIC cycles.