Senior Clocks ASIC Design Engineer - RTL & PPA Innovation

NVIDIA; Austin (TX); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA in Austin, TX is seeking an ASIC clock engineer to own the clock domain across GPU/CPU design. You will optimize PPA, evaluate clocking topologies in RTL, and work with floorplanning and timing teams to enable high-speed clocks.

This role emphasizes collaboration, RTL design, and silicon bringup across cross-disciplinary teams. Must have a BS in Electrical Engineering (MS preferred) and 3+ years' experience in RTL/Verilog, Python, and clocking in advanced chips.

Qualifications

• BS in Electrical Engineering or equivalent; MS preferred.
• 3+ years of relevant work experience.
• Deep understanding of logic optimization and PPA trade-offs.
• RTL design (Verilog), verification and logic synthesis.
• Strong coding skills in Python or similar scripting languages.
• Knowledge of sub-micron silicon issues is a plus.
• Experience with on-chip clocking networks is a bonus.

Responsibilities

• Architect the clock domain to satisfy functional, physical and testing design requirements.
• Collaborate with multiple teams to design GPU/CPU clocks meeting constraints.
• Improve Power, Performance and Area by evaluating DFx, implementation, power and timing.
• Develop clocking solutions with Physical design and timing teams.
• Deliver clock RTL information to verification, timing and DFT teams.
• Participate in end-to-end ASIC execution from micro-arch to silicon bringup.

Skills

RTL design

Verilog

Python scripting

Clock domain design

PPA optimization

Cross-team collaboration

Education

BS in Electrical Engineering

MS preferred

Job description

NVIDIA in Austin, TX is seeking an ASIC clock engineer to own the clock domain across GPU/CPU design. You will optimize PPA, evaluate clocking topologies in RTL, and work with floorplanning and timing teams to enable high-speed clocks.

This role emphasizes collaboration, RTL design, and silicon bringup across cross-disciplinary teams. Must have a BS in Electrical Engineering (MS preferred) and 3+ years' experience in RTL/Verilog, Python, and clocking in advanced chips.