Clocks ASIC Architect – RTL, PPA, Silicon Bringup

NVIDIA; Santa Clara (CA); Hybrid; USD 136,000 - 218,500; Full time

Benefits offered by this job

Equity

Generous benefits package

Job summary

NVIDIA is seeking a talented ASIC engineer to join their clocks team in Santa Clara, CA. You will be responsible for architecting clock domains for GPU and CPU designs. The ideal candidate should have a BS in Electrical Engineering, 3+ years of experience, and skills in RTL design with Verilog.

Competitive salaries offered, starting at $136,000, with a generous benefits package for successful candidates. NVIDIA values diversity and inclusiveness in the workplace. Applications accepted until May 25, 2026.

Qualifications

• 3+ years of relevant work experience.
• Deep understanding of logic optimization techniques and PPA trade-offs.
• Experience in RTL design (Verilog) and verification.

Responsibilities

• Architect clock domain to meet design requirements.
• Engage with teams and design GPU or CPU clocks.
• Improve PPA of NVIDIA chips by evaluating trade-offs.
• Collaborate with teams to develop solutions for high speed Clocking.
• Deliver clock RTL information to verification and timing teams.
• Get involved in end-to-end ASIC execution.

Skills

Logic optimization techniques

Interpersonal skills

RTL design (Verilog)

Python or other scripting languages

Understanding of sub-micron silicon issues

Education

BS in Electrical Engineering or equivalent experience

Tools

Verilog

Job description

NVIDIA is seeking a talented ASIC engineer to join their clocks team in Santa Clara, CA. You will be responsible for architecting clock domains for GPU and CPU designs. The ideal candidate should have a BS in Electrical Engineering, 3+ years of experience, and skills in RTL design with Verilog.

Competitive salaries offered, starting at $136,000, with a generous benefits package for successful candidates. NVIDIA values diversity and inclusiveness in the workplace. Applications accepted until May 25, 2026.