Clocks ASIC Engineer: RTL, PPA & Equity

NVIDIA; Santa Clara (CA); On-site; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA in Santa Clara seeks an ASIC clocking engineer to own clock domain design for GPUs and CPUs. You will collaborate with frontend, floorplan, and silicon teams to craft robust clocking across RTL and physical implementations.

The role focuses on improving Power, Performance, and Area (PPA) while supporting timing closure and end-to-end ASIC flow from micro-architecture to silicon bring-up.

Qualifications

• BS in Electrical Engineering or equivalent experience (MS preferred).
• 2+ years of relevant work experience in ASIC/clocking.
• Deep understanding of logic optimization techniques and PPA trade-offs.
• Excellent interpersonal skills and collaboration across teams.
• Experience in RTL design (Verilog), verification and logic synthesis.
• Strong coding skills in Python or other scripting languages.
• Understanding of sub-micron silicon issues; on-chip clocking knowledge is a bonus.
• Experience with clocking networks and end-to-end ASIC flow is a plus.

Responsibilities

• Architect the clock domain to satisfy functional, physical and testing requirements.
• Engage with multiple teams to design GPU/CPU clocks meeting constraints.
• Improve PPA by evaluating DFx, physical implementation, and timing closure.
• Collaborate with Physical design and timing teams on clocking concerns.
• Deliver clock RTL information to GPU/CPU/SOC verification and DFT teams.
• Contribute to end-to-end ASIC execution from micro-arch to silicon bring-up.

Skills

RTL Design

Verification

Logic Synthesis

Python / Scripting

PPA Trade-offs

Interpersonal Skills

Clocking / On-Chip Clocking

Education

BS in Electrical Engineering

MS preferred

Job description

NVIDIA in Santa Clara seeks an ASIC clocking engineer to own clock domain design for GPUs and CPUs. You will collaborate with frontend, floorplan, and silicon teams to craft robust clocking across RTL and physical implementations.

The role focuses on improving Power, Performance, and Area (PPA) while supporting timing closure and end-to-end ASIC flow from micro-architecture to silicon bring-up.