GPU Clocking Verification Engineer — High-Freq & Equity

NVIDIA; Santa Clara (CA); On-site; USD 116,000 - 190,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking an exceptional ASIC Clocks Verification Engineer in Santa Clara. You will verify high-frequency clock structures and collaborate with ASIC designers, verification engineers, and software teams to optimize clocking for performance and reliability.

You will work with multiple groups to ensure architectural constraints are met, use Perl to boost productivity, and help triage silicon and programming bugs in lab environments.

Qualifications

• Master's degree in Electrical Engineering or equivalent experience.
• Practical experience with SystemVerilog and UVM.
• Experience with Design Verification, Logic Design, and Logic Synthesis.
• Strong coding skills in Python, Perl, or other scripting languages.

Responsibilities

• Collaborate with architects, ASIC designers and verification engineers to verify high frequency clock structures.
• Engage with multiple teams to design GPU clock structure that satisfies architectural constraints.
• Apply general verification principles to verify clock designs.
• Deliver clock information to SOC verification, timing and DFT teams; use Perl to improve productivity.
• Collaborate with Software and product groups to debug GPU clock silicon bugs in new products.
• Understand and design clocking structures to overcome sub-micron design challenges.
• Identify and propose improvements to increase efficiency in GPU clocking design.

Skills

SystemVerilog

UVM

Python

Perl

Logic Design

Design Verification

Logic Synthesis

Education

Master's degree in Electrical Engineering

Job description

NVIDIA is seeking an exceptional ASIC Clocks Verification Engineer in Santa Clara. You will verify high-frequency clock structures and collaborate with ASIC designers, verification engineers, and software teams to optimize clocking for performance and reliability.

You will work with multiple groups to ensure architectural constraints are met, use Perl to boost productivity, and help triage silicon and programming bugs in lab environments.