Clocks ASIC Engineer – Shape GPU/CPU Timing, Equity

NVIDIA Gruppe; Santa Clara (CA); Hybrid; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking an ASIC clocking engineer to shape the clock domain for GPUs and CPUs in Santa Clara. You will work with front-end, floorplanning and back-end teams to optimize PPA and deliver robust clocking solutions in RTL.

The role requires strong Verilog RTL skills, Python scripting, and a good understanding of clock networks and silicon issues. This hybrid position offers equity and comprehensive benefits with competitive base pay.

Qualifications

• BS in Electrical Engineering or equivalent; MS preferred.
• 2+ years of relevant work experience.
• Deep understanding of logic optimization techniques and PPA trade-offs.
• Excellent interpersonal skills and ability to collaborate with multiple teams.
• Experience in RTL design (Verilog), verification and logic synthesis.
• Strong coding skills in Python or other scripting languages.
• Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.
• Implementing on-chip clocking networks is a bonus.

Responsibilities

• Architect the clock domain to satisfy functional, physical and testing design requirements.
• Engage with multiple teams and design GPU/CPU clocks to satisfy architectural, design and physical constraints.
• Improve Power, Performance, and Area (PPA) of NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and timing closure; innovate clocking topologies in RTL.
• Collaborate with Physical design and timing team to evaluate clocking concerns and develop solutions for high speed clocking.
• Deliver clock RTL information to GPU, CPU and SOC verification, timing and DFT teams.
• Participate in end-to-end ASIC execution cycle from micro-arch to silicon bringup.

Skills

Verilog RTL design

Python scripting

PPA trade-offs

Team collaboration

Clocking design

Education

BS in Electrical Engineering

MS preferred

Job description

NVIDIA is seeking an ASIC clocking engineer to shape the clock domain for GPUs and CPUs in Santa Clara. You will work with front-end, floorplanning and back-end teams to optimize PPA and deliver robust clocking solutions in RTL.

The role requires strong Verilog RTL skills, Python scripting, and a good understanding of clock networks and silicon issues. This hybrid position offers equity and comprehensive benefits with competitive base pay.