Senior Analog Timing Architect: PLLs & VCOs

SiTime Corp.; Tempe (AZ); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Quarterly bonus

Equity grants

Equal Opportunity Employer

Job summary

SiTime Corp. seeks a Principal Analog Design Engineer to provide technical leadership in clock and timing products. You will balance performance, schedule and cost while coordinating with test, validation, management and product teams to drive concepts to production in a fast-paced environment.

We value diverse experiences and welcome engineers who can contribute to our mission and collaborate across global teams. Strong communication and lab skills are essential.

Qualifications

• Advanced degree in Electrical Engineering required.
• 10+ years of analog/mixed-signal CMOS design experience.
• Experience designing PLLs and related building blocks.

Responsibilities

• Define, design, and develop innovative timing circuits and products.
• Mentor and guide junior designers across projects.
• Collaborate with remote engineering teams to drive execution.
• Support prototype testing, debugging, and lab characterization.
• Provide technical leadership across the product lifecycle.

Skills

Analog/mixed-signal design

PLL design

Phase detectors and VCOs

SystemVerilog/Verilog-A

Lab testing & characterization

CMOS process knowledge

English communication

Education

Master’s or PhD in Electrical Engineering

Tools

Cadence analog/mixed-signal tools

Job description

SiTime Corp. seeks a Principal Analog Design Engineer to provide technical leadership in clock and timing products. You will balance performance, schedule and cost while coordinating with test, validation, management and product teams to drive concepts to production in a fast-paced environment.

We value diverse experiences and welcome engineers who can contribute to our mission and collaborate across global teams. Strong communication and lab skills are essential.