Principal Analog Design Engineer

SiTime Corp.; Tempe (AZ); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Quarterly bonus

Equity grants

Equal Opportunity Employer

Job summary

SiTime Corp. seeks a Principal Analog Design Engineer to provide technical leadership in clock and timing products. You will balance performance, schedule and cost while coordinating with test, validation, management and product teams to drive concepts to production in a fast-paced environment.

We value diverse experiences and welcome engineers who can contribute to our mission and collaborate across global teams. Strong communication and lab skills are essential.

Qualifications

• Advanced degree in Electrical Engineering required.
• 10+ years of analog/mixed-signal CMOS design experience.
• Experience designing PLLs and related building blocks.

Responsibilities

• Define, design, and develop innovative timing circuits and products.
• Mentor and guide junior designers across projects.
• Collaborate with remote engineering teams to drive execution.
• Support prototype testing, debugging, and lab characterization.
• Provide technical leadership across the product lifecycle.

Skills

Analog/mixed-signal design

PLL design

Phase detectors and VCOs

SystemVerilog/Verilog-A

Lab testing & characterization

CMOS process knowledge

English communication

Education

Master’s or PhD in Electrical Engineering

Tools

Cadence analog/mixed-signal tools

Job description

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com .

Job Summary

SiTime is seeking a Principal Analog Design Engineer to provide technical leadership in developing advanced clock and timing products. This role combines hands‑on circuit design expertise with strong system‑level understanding to balance performance, schedule, and cost trade‑offs. Working closely with test and validation, program management, product engineering, and other functional teams, you will align technical solutions with business goals and drive projects from concept through successful execution in a collaborative, fast‑paced environment.

We value diverse experiences, perspectives, and career paths, and welcome candidates who are excited to contribute to our mission.

Responsibilities:

• Define, design, and develop innovative circuits for high-performance timing products
• Mentor, lead, and guide junior designers
• Collaborate effectively with remote engineering teams
• Support prototype testing, debugging, and lab characterization
• Provide technical support across the full product development cycle through production release

Qualifications & Requirements:

• Master’s or PhD degree in Electrical Engineering
• 10+ years of relevant experience in analog/mixed-signal CMOS design
• Strong knowledge of integrated circuit design, device physics, and process technology
• Experience designing Phase Locked Loops (PLLs) or related building blocks, including phase detectors, charge pumps, LC-Voltage Controlled Oscillators (VCOs), fractional-N synthesizers, crystal oscillators, VCXOs, temperature sensors, on-chip regulators, DACs, ADCs and similar circuits
• Deep understanding of transistor behavior, circuit noise theory, and phase noise concepts
• Proficiency with the Cadence analog/mixed-signal simulation toolset
• Familiarity with analog/mixed-signal design flow, simulation methods, design rules, post‑layout verification
• Experience with analog behavioral modeling using SystemVerilog, Verilog-A, or AMS
• Hands‑on experience with lab testing and characterization
• English proficiency is required, including the ability to effectively communicate, collaborate, and perform job responsibilities in a professional business environment.

It is not necessary to meet all job requirements to be a qualified candidate for the position.

Desired Characteristics & Attributes:

• Collaborative, self‑motivated, and positive team contributor
• Able to empower others and provide effective mentorship
• Strong analytical and problem‑solving skills

Compensation Range: (For HR only)

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.

In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.

SiTime is an Equal Opportunity Employer . We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verifyprogram.

Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.

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