Senior Analog Layout Architect - Chip-Level, Global

SiTime Corp.; Santa Clara (CA); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

401k plan

Health and wellness program (medical,*

Job summary

SiTime uses MEMS-based precision timing and offers a challenging Senior Layout Design Engineer role in California. You will lead top-chip and block-level analog layout for CMOS/BiCMOS, coordinate offshore teams, and help establish standard methodologies to ensure high-quality layouts.

The position requires 15+ years of layout experience, proficiency with Cadence Virtuoso and DRC/LVS/ERC workflows, and the ability to mentor engineers while driving tape-out and integration across sites.

Qualifications

• 15+ years of analog and full-custom digital layout experience.
• ,

Responsibilities

• Collaborate remotely with design teams across centers and time zones.
• Lead layout at chip and block levels for CMOS/BiCMOS.
• Execute schematic-driven layout adhering to constraints.
• Develop floor plans, power distribution, shielding, and device-matching layouts.
• Verify layouts and sign off with DRC/LVS/ERC.
• Own tape-out activities and chip-chip integration.
• Mentor junior engineers and offshore contractors.
• Contribute to common best practices across sites.

Skills

15+ years experience in analog andfull

Cadence Virtuoso

DRC LVS ERC debugging - Cadence PVS

Parasitics matching crosstalk EMI

Device matching electromigration power

Chip-level floorplanning analog block

Chip-level integration tape-out

Automation scripting productivity

Physical lifting up to 5 lbs

Education

BA/BS degree in Layout Design or related field

Tools

Cadence Virtuoso

Cadence PVS

Mentor Calibre

Job description

SiTime uses MEMS-based precision timing and offers a challenging Senior Layout Design Engineer role in California. You will lead top-chip and block-level analog layout for CMOS/BiCMOS, coordinate offshore teams, and help establish standard methodologies to ensure high-quality layouts.

The position requires 15+ years of layout experience, proficiency with Cadence Virtuoso and DRC/LVS/ERC workflows, and the ability to mentor engineers while driving tape-out and integration across sites.