Principal Analog Layout Engineer - Equity Eligible

SiTime Corp.; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

401k plan

Health insurance

Dental

Vision

Equity grants

Quarterly bonus

Job summary

SiTime Corp. in Santa Clara, CA seeks a Senior Layout Design Engineer to lead top‑chip and block‑level analog layout for CMOS/BiCMOS circuits. You will coordinate with offshore designers, mentor juniors, and help develop standard methodologies across sites.

You will develop floorplans, power distribution, and device‑matching layouts, verify DRC/LVS/ERC, and own chip‑level integration and tape‑out while advancing best practices.

Qualifications

• BA/BS in Layout Design or related field, or equivalent experience.
• 15+ years in layout design for analog and full-custom digital blocks.
• Experience with TSMC 180nm, 65nm, 22nm process technologies.
• Proficiency with Cadence Virtuoso tools.
• Knowledge of DRC/LVS/ERC debugging with PVS or Calibre.
• Understanding of layout concepts: parasitics, matching, crosstalk, EM, NTN isolation.
• Ability to meet area constraints while solving device matching and power distribution challenges.
• Experience with chip-level floorplanning, integration, and tape-out.
• Ability to automate workflows with scripts.
• Must be able to lift up to 5 lbs.

Responsibilities

• Collaborate remotely with global design teams across multiple centers.
• Lead and perform custom analog layout design at chip and block levels.
• Execute schematic-driven layout adhering to constraints.
• Create area-efficient functional block layouts meeting circuit requirements.
• Develop top-chip floorplans, power distribution networks, shielding structures, and device-matching layouts.
• Verify layouts with DRC, LVS, and ERC signoff.
• Perform chip-level routing and layout-related tasks.
• Own chip-level integration, verification, and tape-out.
• Train and mentor junior layout engineers and offshore contractors.
• Contribute to standard best practices and workflows across sites.
• Help establish and improve processes to achieve high layout quality.

Skills

Layout design

Analog design

Full-custom digital blocks

Education

BA/BS in Layout Design or related field

Tools

Cadence Virtuoso

PVS

Mentor Calibre

Job description

SiTime Corp. in Santa Clara, CA seeks a Senior Layout Design Engineer to lead top‑chip and block‑level analog layout for CMOS/BiCMOS circuits. You will coordinate with offshore designers, mentor juniors, and help develop standard methodologies across sites.

You will develop floorplans, power distribution, and device‑matching layouts, verify DRC/LVS/ERC, and own chip‑level integration and tape‑out while advancing best practices.