Principal Analog Design Engineer – Clock & Timing Leader

SiTime Corp.; United States; On-site; USD 190,000 - 260,000; Full time

Benefits offered by this job

Equity grants

Annual bonus

401k plan

Health / dental / vision

Job summary

SiTime is seeking a Principal Analog Design Engineer to provide technical leadership in developing advanced clock and timing products. This role balances hands-on circuit design with system-level judgment to meet performance, schedule, and cost targets in collaboration with test, validation, and product teams.

You will mentor junior designers and work with remote teams to drive projects from concept through production.

Qualifications

• Master’s or PhD in Electrical Engineering.
• 10+ years of analog/mixed-signal CMOS design experience.
• Deep understanding of transistor behavior, circuit noise theory, and phase noise concepts.

Responsibilities

• Define, design, and develop novel circuits for high-performance timing products.
• Mentor, lead, and guide junior designers.
• Collaborate effectively with remote engineering teams.
• Support prototype testing, debugging, and lab characterization.
• Provide technical support across the full product development cycle through production release.

Skills

Analog/mixed-signal design

PLL design

Circuit design expertise

SystemVerilog/Verilog-A/AMS

Lab testing & characterization

Cadence tools

transistor behavior & noise theory

Education

Master’s or PhD in Electrical Engineering

Tools

Cadence ASL/AMS

Job description

SiTime is seeking a Principal Analog Design Engineer to provide technical leadership in developing advanced clock and timing products. This role balances hands-on circuit design with system-level judgment to meet performance, schedule, and cost targets in collaboration with test, validation, and product teams.

You will mentor junior designers and work with remote teams to drive projects from concept through production.