Senior Analog & RF IC Layout Engineer – Onsite

The Ash Group; Irvine (CA); On-site; USD 149,000 - 182,000; Full time

Benefits offered by this job

Medical insurance

Dental Insurance

Vision Insurance

401(k) matching

ESPP

Employee Assistance Program

Paid holidays

Paid sick leave

Paid vacation

Job summary

The Ash Group is seeking an Analog & RF IC Senior Layout Engineer to join our team in Irvine or San Diego, CA. You will translate schematics into physical layouts for high-speed IP blocks using Cadence Virtuoso on advanced FinFET nodes, collaborating closely with senior designers on floor planning and power/ground strategies.

Ideal candidates hold a BS or MS in Electrical Engineering with substantial hands-on layout experience and mastery of DRC/LVS flows using Virtuoso and Calibre verification.

Qualifications

• BS in Electrical Engineering with 8+ years of related experience or MS with 6+ years of related experience.
• Extensive layout experience for high-speed analog/digital circuits (TX/RX/SerDes/PLLs).
• Proficient in Cadence Virtuoso suite, including VXL layout and Mentor Calibre verification.
• Design and layout experience on advanced FinFET nodes required.
• Strong fundamentals in layout and ability to solve complex circuit layout challenges.

Responsibilities

• Translate schematics into DRC/LVS-clean layouts for critical IP blocks.
• Collaborate with senior designers on floor planning, power/ground, and device matching.
• Utilize industry-standard EDA tools on advanced process nodes (FinFET and beyond).
• Contribute to project schedules and top-level integration for product roadmaps.

Skills

High-speed analog/digital layout

FinFET node experience

Circuit layout troubleshooting

Device matching collaboration

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Cadence Virtuoso

Virtuoso VXL

Mentor Calibre verification

Job description

The Ash Group is seeking an Analog & RF IC Senior Layout Engineer to join our team in Irvine or San Diego, CA. You will translate schematics into physical layouts for high-speed IP blocks using Cadence Virtuoso on advanced FinFET nodes, collaborating closely with senior designers on floor planning and power/ground strategies.

Ideal candidates hold a BS or MS in Electrical Engineering with substantial hands-on layout experience and mastery of DRC/LVS flows using Virtuoso and Calibre verification.