IC Layout Engineer – High‑Speed Analog & SoC IP (Irvine)

MediaTek Research Lab Inc.; Irvine (CA); On-site; USD 85,900 - 137,500; Full time

Benefits offered by this job

Comprehensive health insurance

401(k) plan

Paid time off (PTO)

Job summary

MediaTek Research Lab Inc. is looking for an Analog Layout Engineer in Irvine, California. The role involves developing high-quality layouts for data-converters and power management circuitry, and performing layout in CMOS or FinFET technologies.

Candidates should be proficient in Virtuoso and Calibre tools, with experience in high-speed circuits, and knowledge of N7/N5/N3 processes. Competitive compensation and benefits are offered, including health insurance and a 401(k) plan.

Qualifications

• Proficient in Virtuoso and Calibre tools.
• Familiar with validating LVS/DRC/ERC/ANT/ESD/LPE.
• Layout experience in high-speed circuits, hybrid circuits, low-dropout regulators, phase-locked loops and ESD.
• Knowledge of N7/N5/N3 processes.

Responsibilities

• Work closely with the design team to develop high-quality layouts for various IP.
• Perform layout in CMOS or FinFET technologies for high-speed front ends.
• Design layout, verification, parasitic extraction using the Cadence design environment.

Skills

Proficient in Virtuoso and Calibre tools

Validating LVS/DRC/ERC/ANT/ESD/LPE

Layout experience in high-speed circuits

Knowledge of N7/N5/N3 processes

Job description

MediaTek Research Lab Inc. is looking for an Analog Layout Engineer in Irvine, California. The role involves developing high-quality layouts for data-converters and power management circuitry, and performing layout in CMOS or FinFET technologies.

Candidates should be proficient in Virtuoso and Calibre tools, with experience in high-speed circuits, and knowledge of N7/N5/N3 processes. Competitive compensation and benefits are offered, including health insurance and a 401(k) plan.