Senior Analog IC Layout Engineer – Tapeout & Verification Lead

Elevate; San Diego (CA); On-site; USD 145,000 - 175,000; Full time

Job summary

Elevate in San Diego seeks a Staff Analog Layout Engineer to own the physical layout and verification of advanced analog and mixed-signal ICs for the ATE market. You will work across block-level and full-chip layouts using 65nm to 100+V BCD processes.

You will collaborate with analog design teams to optimize area, performance, and reliability, perform LVS/DRC checks, and drive tapeouts while mentoring engineers on best practices and layout flows.

Qualifications

• Bachelor’s degree in Electrical Engineering or a related field.
• 8+ years of analog/mixed-signal IC layout experience.
• Strong understanding of analog CMOS circuits and device physics.
• Experience with LVS/DRC verification and manufacturability.

Responsibilities

• Perform physical layout of analog and mixed-signal ICs at block and full-chip levels.
• Develop floorplans and optimize placement for area, performance, and power.
• Verify LVS and DRC to ensure layout accuracy and process-rule compliance.
• Collaborate with design engineers to translate circuit requirements into layouts.
• Partner with cross-functional teams to optimize chip performance and tapeouts.
• Troubleshoot layout, verification, and manufacturability issues.

Skills

Analog layout

IC design knowledge

LVS/DRC verification

EDA tools

Device physics

Layout optimization

Scripting SKILL

Education

Bachelors in Electrical Engineering

Tools

Cadence

Mentor Graphics

Tanner

Calibre

Job description

Elevate in San Diego seeks a Staff Analog Layout Engineer to own the physical layout and verification of advanced analog and mixed-signal ICs for the ATE market. You will work across block-level and full-chip layouts using 65nm to 100+V BCD processes.

You will collaborate with analog design teams to optimize area, performance, and reliability, perform LVS/DRC checks, and drive tapeouts while mentoring engineers on best practices and layout flows.