Analog IC Layout Engineer

Technical-Link N. America; California (MO); On-site; USD 110,208 - 123,984; Full time

Job summary

A leading semiconductor manufacturing company is seeking a Mid-Senior Level Analog Layout Designer in California. The role involves working on high-frequency analog and custom digital circuits, requiring 6-8+ years of experience and proficiency with tools like Cadence Virtuoso. Candidates should have a Bachelor of Science degree and a solid understanding of analog layout concepts. This contract position offers an hourly pay range of $80-$90, reflecting the successful candidates' expertise and efficiency.

Qualifications

• 6-8+ years of hands-on experience in Analog or RF layout.
• Experience with analog modules such as SerDes, ADCs/DACs, and PLLs is a plus.
• Good understanding of analog layout concepts for deep sub-micron processes.

Responsibilities

• Work independently on Analog layout design coordinating with circuit designers.
• Work with both design engineers and mask design engineers in remote locations.
• Understand and implement design requests including pwr/gnd nets and critical device matching.

Skills

Independent work on block level and IP level Analog layout design

Coordination with circuit designers

High-frequency analog layout experience

Understanding of ESD concepts

Good communication skills

Experience with Cadence Virtuoso

Basic Unix scripting

Education

Bachelor of Science degree

Tools

Cadence Virtuoso

Calibre LVS and DRC tools

Job description

Technical-Link N. America provided pay range

This range is provided by Technical-Link N. America. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$80.00/hr - $90.00/hr

Job Responsibilities and Qualifications

The candidate should be able to work independently on block level and IP level Analog layout design, coordinating with the circuit designer and the rest of the layout team. The candidate will need to be able to work with both design engineers and mask design engineers in remote locations, and thus the ability to plan and efficiently use email and Webex to review critical aspects of the layout work is essential to this role.

The candidate should have experience with the layout of high-frequency analog and high-speed custom digital circuits in which parasitic minimization is critical.

The candidate should be able to understand how to implement design requests including pwr/gnd nets, critical device matching, and sensitive signal routing. They should be able to recognize how decisions at their level of integration affect the design hierarchy above and below their level. They should have a good understanding of ESD concepts, including how to best use guard rings for design isolation.

The candidate should be comfortable asking questions of the rest of the layout team; they will be expected to share items that they feel may help others.

The candidate should have experience in using Cadence Virtuoso and also the Calibre LVS and DRC checking tools. Some expertise in basic Unix scripting is a plus.

Candidate should have minimum 6‑8+ years of hands‑on experience in Analog or RF layout. Experience with analog modules such as SerDes, ADCs/DACs, and PLLs is a plus. Candidate should have a good understanding of analog layout concepts for deep sub‑micron processes and knowledge of fabrication process, and experience in layout in FinFET technologies is required. Preference will be given for candidates with experience in 7nm and 5nm process nodes.

Education should include a Bachelor of Science degree.

Seniority Level

Mid‑Senior level

Employment Type

Contract

Industry

Semiconductor Manufacturing

Location

Sunnyvale, CA