Senior Analog/RF Layout Engineer – Onsite in Santa Clara

Capgemini Engineering; Santa Clara (CA); On-site; USD 98,000 - 204,000; Full time

Benefits offered by this job

Medical, dental, vision

401(k) retirement plan

Paid time off

Life and disability insurance

Job summary

Capgemini Engineering is seeking an experienced Analog/RF Layout Designer for onsite support in Santa Clara, CA. You will own block- and IP-level layouts, floorplanning, routing, and top-level integration across analog/mixed-signal blocks in cutting-edge FinFET processes.

You will join a global design organization and mentor teammates while addressing DRC/LVS and EMI/ESD considerations to ensure high-quality tape-outs and reliable silicon performance.

Qualifications

• 6+ years of hands-on analog/RF layout design (8+ years preferred).
• Experience with analog floor planning for complex modules such as SerDes, ADC/DAC, PLLs.
• Strong understanding of analog layout best practices for deep sub-micron CMOS and FinFET technologies.
• Ability to resolve DRC/LVS/antenna issues and mentor team members.

Responsibilities

• Develop block-level and IP-level analog/RF layouts from concept to tape-out.
• Own floorplanning, placement, routing, and optimization for analog/mixed-signal blocks.
• Lead top-level integration of multiple analog/mixed-signal blocks within larger SoCs.
• Apply deep expertise in advanced deep sub-micron and FinFET process technologies, incorporating fabrication, EM, ESD, latch-up, and reliability considerations into layouts.
• Mentor team and guide other engineers as a technical lead.

Skills

Analog RF layout

Floor planning

Layout optimization

SerDes/PLL/ADC/DAC

FinFET tech

Cross-functional collaboration

Education

Bachelor’s degree in Electrical Engineering

Job description

Capgemini Engineering is seeking an experienced Analog/RF Layout Designer for onsite support in Santa Clara, CA. You will own block- and IP-level layouts, floorplanning, routing, and top-level integration across analog/mixed-signal blocks in cutting-edge FinFET processes.

You will join a global design organization and mentor teammates while addressing DRC/LVS and EMI/ESD considerations to ensure high-quality tape-outs and reliable silicon performance.