Senior Analog & RF Layout Engineer

Capgemini; San Francisco, Santa Clara (CA, CA); On-site; USD 98,000 - 204,000; Full time

Job summary

Capgemini is seeking an experienced Analog / RF Layout Designer to provide onsite support for advanced semiconductor nodes in San Francisco and Santa Clara. You will independently develop block-level and IP-level analog/RF layouts, drive floorplanning, placement, and routing, and lead top-level integration across SoCs.

You will apply deep expertise in FinFET and deep sub-micron processes, addressing fabrication, EM, ESD, latch-up and reliability concerns while collaborating with global teams and

Qualifications

• Bachelor’s degree in Electrical Engineering or related field.
• 6+ years of hands-on analog and/or RF layout experience (8+ years preferred).
• Proven experience with analog floor planning and layout for complex modules such as SerDes, ADC/DAC, PLLs.
• Strong understanding of analog layout best practices for deep sub-micron CMOS and FinFET technologies.

Responsibilities

• Independently develop block-level and IP-level analog/RF layouts, collaborating with circuit designers and global teams.
• Own floorplanning, placement, routing, and optimization for complex analog/mixed-signal blocks.
• Lead and support top-level integration of multiple analog/mixed-signal blocks within larger SoCs.
• Apply expertise in FinFET and deep sub-micron processes, considering fabrication, EM, ESD, latch-up and reliability.
• Resolve DRC/LVS/antenna/verification issues and mentor team members as a technical lead.

Skills

Analog layout

RF layout

Floorplanning

Placement

Routing

Top-level integration

DRC/LVS

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence

Calibre

Job description

Capgemini is seeking an experienced Analog / RF Layout Designer to provide onsite support for advanced semiconductor nodes in San Francisco and Santa Clara. You will independently develop block-level and IP-level analog/RF layouts, drive floorplanning, placement, and routing, and lead top-level integration across SoCs.

You will apply deep expertise in FinFET and deep sub-micron processes, addressing fabrication, EM, ESD, latch-up and reliability concerns while collaborating with global teams and