Analog & RF IC Senior Layout Engineer

The Ash Group; Irvine (CA); On-site; USD 149,000 - 182,000; Full time

Benefits offered by this job

Medical insurance

Dental Insurance

Vision Insurance

401(k) matching

ESPP

Employee Assistance Program

Paid holidays

Paid sick leave

Paid vacation

Job summary

The Ash Group is seeking an Analog & RF IC Senior Layout Engineer to join our team in Irvine or San Diego, CA. You will translate schematics into physical layouts for high-speed IP blocks using Cadence Virtuoso on advanced FinFET nodes, collaborating closely with senior designers on floor planning and power/ground strategies.

Ideal candidates hold a BS or MS in Electrical Engineering with substantial hands-on layout experience and mastery of DRC/LVS flows using Virtuoso and Calibre verification.

Qualifications

• BS in Electrical Engineering with 8+ years of related experience or MS with 6+ years of related experience.
• Extensive layout experience for high-speed analog/digital circuits (TX/RX/SerDes/PLLs).
• Proficient in Cadence Virtuoso suite, including VXL layout and Mentor Calibre verification.
• Design and layout experience on advanced FinFET nodes required.
• Strong fundamentals in layout and ability to solve complex circuit layout challenges.

Responsibilities

• Translate schematics into DRC/LVS-clean layouts for critical IP blocks.
• Collaborate with senior designers on floor planning, power/ground, and device matching.
• Utilize industry-standard EDA tools on advanced process nodes (FinFET and beyond).
• Contribute to project schedules and top-level integration for product roadmaps.

Skills

High-speed analog/digital layout

FinFET node experience

Circuit layout troubleshooting

Device matching collaboration

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Cadence Virtuoso

Virtuoso VXL

Mentor Calibre verification

Job description

*** US Citizens or Green Card Holder Only. No 3rd Parties ***

Summary

The Ash Group is hiring an Analog & RF IC Senior Layout Engineer (24629) for our client, a global technology powerhouse supplying semiconductor and infrastructure software products for the world's leading networks. This is a fulltime position working in Irvine or San Diego, CA (Onsite). We are offering a salary up to 165K based on skill set.

• Compensation: Up to $165K W2
• Benefits: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

What You’ll Be Doing

• Join an industry-leading team of innovators to build the next generation of high-tech hardware. As an Analog/RF Layout Engineer, you won’t just watch from the sidelines—you'll be in the trenches of custom IP block design, translating complex schematics into physical reality on the world’s most advanced process nodes.
• Bridge the Gap: Translate circuit schematics into DRC/LVS-clean layouts for critical IP blocks.
• Collaborate & Strategize: Partner with senior designers on floor planning, power/ground architecture, and precision device matching.
• Master the Tools: Leverage industry-standard EDA tools and cutting-edge technology nodes (FinFET and beyond).
• Impact the Roadmap: Participate in schedule assessments and top-level integration for projects that define our products' success.

What We’re Looking For

• A BS degree in Electrical Engineering (or a related field) with 8+ years of related experience, OR an MS degree in Electrical Engineering (or a related field) with 6+ years of related experience is required
• Extensive experience with the layout of high-speed custom analog and digital circuits (e.g., TX, RX, SerDes, and PLLs) is a must
• Deep familiarity with the Cadence Virtuoso tool suite for designing and verifying high-speed custom circuits, including the Virtuoso VXL layout suite and Mentor Calibre verification.
• Proven design and layout experience in advanced FinFET nodes is required.
• A wide-ranging track record demonstrating both a thorough understanding of layout fundamentals and the creativity needed to solve complex circuit layout challenges.