Senior Mixed-Signal RF Verification Engineer

Apple Inc.; Austin, Northern (TX, KY); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Apple Inc. is seeking a Design Verification Engineer to own RNM/SystemVerilog behavioral modeling and verification of analog/RF blocks inside a large SoC. You will collaborate with Analog designers and set up AMS simulation environments to ensure accurate verification results.

The role requires strong background in analog/RF theory, hands-on experience with Cadence mixed-signal tools, reading analog schematics, and the ability to model high-frequency PLLs. This position is based in Austin, TX.

Qualifications

• BS and minimum 10 years of relevant industry experience.
• Strong fundamentals in analog/RF circuit theory/topologies.
• Experience with RNM/SystemVerilog modeling and verification.

Responsibilities

• Develop RNM RF/Analog models in SystemVerilog.
• Develop models with self-checking techniques.
• Assess model accuracy per verification goals.
• Create assertions to ensure specs are respected and provide verification criteria.
• Collaborate with Analog designers to set up AMS simulation.

Skills

SystemVerilog

Analog RF theory

AMS verification

Debugging

Education

BS or higher

MSc with 7+ years

Tools

Cadence mixed signal

Job description

Apple Inc. is seeking a Design Verification Engineer to own RNM/SystemVerilog behavioral modeling and verification of analog/RF blocks inside a large SoC. You will collaborate with Analog designers and set up AMS simulation environments to ensure accurate verification results.

The role requires strong background in analog/RF theory, hands-on experience with Cadence mixed-signal tools, reading analog schematics, and the ability to model high-frequency PLLs. This position is based in Austin, TX.