DV - Staff (+) Verification Engineer- AMS modeling

eliyan; San Francisco (CA); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Excellent benefits

On-site work

Job summary

Eliyan is seeking an experienced Verification Engineer to join our fast-growing chiplet startup in San Francisco. You will lead the verification of Serdes and develop RNM AMS SystemVerilog models for PHYs, collaborating with the analog and design teams.

This hands-on role requires strong SystemVerilog, UVM, and mixed-signal IP verification skills, with on-site work M-F in a dynamic environment that offers excellent benefits.

Qualifications

• BS in EE or related field required.
• 5+ years of relevant verification experience.
• Deep analog design expertise.
• Strong SystemVerilog/UVM test environment and assertion coding.
• Experience verifying mixed-signal IPs.

Responsibilities

• Develop and execute RNM AMS model for best in class PHYs.
• Make sure the quality of models reflects schematics.
• Write and debug SystemVerilog/UVM compliant test cases
• Collaborate with design team to ensure design quality
• Expertise to understand analog blocks.

Skills

Analog design expertise

SystemVerilog/UVM

Mixed-signal IP verification

Scripting: Python/Perl/Tcl

Formal verification (JasperGold/vc‑f o

Education

BS in EE or related field

Tools

Jasper Gold

vc-formal

Job description

Join the leading chiplet startup! As an Eliyan Verification Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead the verification of Serdes. You will be developing state-of-the-art AMS systemVerilog models (RNM) for best-in-class PHYs. You will own verification of AMS SystemVerilog models. This is a hands-on technical role. You'll work with analog team, look at schematics and write the RNM models. We offer a fun work environment with excellent benefits. We offer a fun work environment with excellent benefits. ONSITE M-F.

• Develop and execute RNM AMS model for best in class PHYs.
• Make sure the quality of models reflects schemetics.
• Write and debug SystemVerilog/UVM compliant test cases
• Collaborate with design team to ensure design quality
• Expertise to understand analog blocks.

• 5+yrs relevant experience
• BS in EE or related field.
• Deepanalog design expertise
• Knowledge of SystemVerilog, test environment and assertion coding
• Experience in verifying mixed signal IPs

• Experience with Formal verification with Jasper Gold or vc-formal
• Python/Perl/Tclscripting for design verification