Senior Analog Layout Lead – CMOS/BiCMOS

Sitime-Corporation; United States; On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Quarterly bonus

Equity grants

Job summary

SiTime in the United States seeks a Senior Layout Design Engineer to lead top-chip, block-level and custom Analog Layout for CMOS and BiCMOS circuits. You will review work from offshore designers, mentor junior engineers and help establish standard layout methodologies across sites.

You will develop floor plans, power distribution, device matching layouts, verify DRC/LVS/ERC, and own tape-out activities while collaborating with global teams to ensure high-quality layouts and on-time delivery.

Qualifications

• 8+ years of layout design experience for analog and full-custom digital blocks.
• Experience with CMOS/BiCMOS layouts and parasitics, matching and EM considerations.
• Proficiency with DRC/LVS/ERC debugging and layout verification tools.

Responsibilities

• Lead top-chip, block-level, and custom analog layout design for CMOS/BiCMOS circuits.
• Coordinate with offshore layout teams and mentor junior engineers.
• Develop floor plans, power distribution, and device-matching layouts; ensure DRC/LVS/ERC signoffs.

Skills

Analog layout design

Full-custom digital blocks

Team collaboration

Schematic-driven layout

Education

BA/BS in Layout Design or related field

Equivalent experience

Tools

Cadence Virtuoso

Cadence PVS

Mentor Calibre

Job description

SiTime in the United States seeks a Senior Layout Design Engineer to lead top-chip, block-level and custom Analog Layout for CMOS and BiCMOS circuits. You will review work from offshore designers, mentor junior engineers and help establish standard layout methodologies across sites.

You will develop floor plans, power distribution, device matching layouts, verify DRC/LVS/ERC, and own tape-out activities while collaborating with global teams to ensure high-quality layouts and on-time delivery.