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IntelliPro is seeking an Analog Layout Engineer to lead full-chip and block-level layouts for power management ICs in a bilingual, cross‑continent team. You will translate discussions between US and China teams, place devices with attention to matching and thermal performance, and ensure clean DRC/LVS/ERC results.
Qualified applicants bring 5+ years in analog/mixed-signal layout on 55–90nm nodes, Cadence Virtuoso experience, and Mandarin-English fluency to communicate across time zones.
IntelliPro is seeking an Analog Layout Engineer to lead full-chip and block-level layouts for power management ICs in a bilingual, cross‑continent team. You will translate discussions between US and China teams, place devices with attention to matching and thermal performance, and ensure clean DRC/LVS/ERC results.
Qualified applicants bring 5+ years in analog/mixed-signal layout on 55–90nm nodes, Cadence Virtuoso experience, and Mandarin-English fluency to communicate across time zones.