Senior Analog Layout Design Lead – Global Collaboration

SiTime; Santa Clara (CA); On-site; USD 125,000 - 172,000; Full time

Benefits offered by this job

Equity grants

401k plan

Health benefits

Job summary

SiTime is seeking a Senior Layout Design Engineer to lead top-chip and block-level analog layout for CMOS and BiCMOS circuits. You will coordinate work with offshore teams, mentor junior layout engineers, and help establish standard methodologies to ensure high-quality layouts across sites.

The role requires extensive experience with advanced process technologies and Cadence tools, with a focus on achieving tight layout quality and successful tape-out.

Qualifications

• BA/BS degree in Layout Design or related field.
• 15+ years of experience in analog and full-custom digital layout.
• Experience with TSMC 180nm, 65nm, 22nm process technologies.
• Proficiency with Cadence Virtuoso and DRC/LVS/ERC debugging tools.

Responsibilities

• Collaborate remotely with local and global design and layout teams across multiple centers and time zones.
• Lead and perform custom analog layout design at chip and block levels for CMOS and BiCMOS circuits.
• Execute schematic-driven layout design while adhering to design constraints.
• Create area-efficient functional block layouts that meet circuit design requirements.
• Develop top-chip and block-level floor plans, power distribution networks, shielding structures, and device-matching layouts.
• Verify layouts and ensure successful DRC, LVS, and ERC signoff.
• Own chip-level routing and other layout-related activities.
• Own chip-chip integration, verification, and tape-out activities.
• Provide support for additional projects as required by management.
• Train and mentor junior layout engineers and offshore contractors.
• Contribute to development of best practices and workflows across sites.
• Help establish and improve processes to achieve high layout quality.

Skills

Layout design

Analog layout

Cadence Virtuoso

DRC/LVS/ERC debugging

Chip floorplanning

Education

BA/BS in Layout Design or related field

Tools

Cadence Virtuoso

Cadence PVS

Mentor Calibre

Job description

SiTime is seeking a Senior Layout Design Engineer to lead top-chip and block-level analog layout for CMOS and BiCMOS circuits. You will coordinate work with offshore teams, mentor junior layout engineers, and help establish standard methodologies to ensure high-quality layouts across sites.

The role requires extensive experience with advanced process technologies and Cadence tools, with a focus on achieving tight layout quality and successful tape-out.