Senior Analog IC Layout Engineer - Tapeout Specialist

Elevate Semiconductor; San Diego (CA); On-site; USD 145,000 - 175,000; Full time

Job summary

Elevate Semiconductor seeks a Staff Analog Layout Engineer to own the physical layout and verification of complex analog/mixed-signals for the ATE market. You will work across block-level and full-chip layouts across 65nm to 100+V BCD processes.

You will collaborate with analog design engineers to drive layout strategy, applying expertise in matching, parasitics, reliability and manufacturability while guiding tapeouts.

Qualifications

• Bachelor's degree in Electrical Engineering or related field required.
• Minimum of 8 years of professional experience in analog and mixed-signal IC layout design.
• Strong understanding of analog CMOS circuits and device physics.
• Solid knowledge of IC design, qualification, and manufacturing lifecycle.
• Hands-on experience with industry-standard EDA tools such as Cadence, Mentor Graphics, or Tanner.
• Proficiency in LVS and DRC verification using Cadence or Mentor tools.

Responsibilities

• Perform physical layout of analog and mixed-signal ICs at block and full-chip levels.
• Develop floorplans and optimize component placement for area, performance, and power.
• Perform LVS and DRC verification to ensure layout accuracy and compliance with process rules.
• Collaborate with design engineers to translate circuit requirements into high-quality layouts.
• Partner with digital design, packaging, and cross-functional teams to optimize chip performance.
• Troubleshoot and resolve layout, verification, and manufacturability issues.

Skills

Analog IC layout

LVS/DRC verification

EDA tools proficiency

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence

Mentor Graphics

Tanner EDA

Job description

Elevate Semiconductor seeks a Staff Analog Layout Engineer to own the physical layout and verification of complex analog/mixed-signals for the ATE market. You will work across block-level and full-chip layouts across 65nm to 100+V BCD processes.

You will collaborate with analog design engineers to drive layout strategy, applying expertise in matching, parasitics, reliability and manufacturability while guiding tapeouts.