Lead High-Speed Analog Layout Architect

Socket.dev; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Socket.dev seeks a Senior/Principal Analog Layout Engineer to drive layout design for analog and mixed-signal IP blocks central to our optical communication platforms. You will lead blocks like ADCs/DACs/PLLs and mentor teammates while interfacing with CAD/PDK teams to ensure first-pass silicon success.

You will own floor planning, routing, and signoff checks, collaborating with circuit designers to optimize performance and reliability across multi-time-zone teams and automation efforts.

Qualifications

• Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies.
• Proven track record of top-level IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred).
• Experience with LVS, DRC, PERC, ERC, and related signoff checks; ability to lead layout reviews.

Responsibilities

• Lead the physical layout design of complex analog/mixed-signal macros from floor planning through final verification.
• Collaborate with schematic designers to optimize performance, matching, symmetry, and reliability.
• Mentor junior layout engineers/contractors across time zones; enforce best practices in layout design and verification.

Skills

Analog/mixed-signal layout

Mentoring

Layout verification

Layout performance optimization

Documentation & communication

Tools

Cadence Virtuoso

Calibre

Pegasus

Job description

Socket.dev seeks a Senior/Principal Analog Layout Engineer to drive layout design for analog and mixed-signal IP blocks central to our optical communication platforms. You will lead blocks like ADCs/DACs/PLLs and mentor teammates while interfacing with CAD/PDK teams to ensure first-pass silicon success.

You will own floor planning, routing, and signoff checks, collaborating with circuit designers to optimize performance and reliability across multi-time-zone teams and automation efforts.