Senior Analog IC Design Engineer — Tapeout Leader

Zenovo; Boston (MA); On-site; USD 150,000 - 210,000; Full time

Job summary

Zenovo is seeking a Senior Engineer to join their silicon team and drive the next generation of chips. You’ll own block‑level circuit design from architecture and simulation through implementation and tape‑out, tackling analog and mixed‑signal challenges across ADCs, PLLs, regulators and high‑speed circuits.

You’ll collaborate with architecture, layout and verification teams in a hands‑on, on‑site environment, with multiple tape‑outs and a path to system‑level impact.

Qualifications

• 6+ years in analog/mixed-signal IC design.
• Multiple tape-outs required.
• Experience with ADCs, PLLs, regulators or high-speed circuits.
• Strong Cadence experience.
• Hands-on layout experience is desirable.
• MS or PhD in Electrical Engineering preferred.

Responsibilities

• Own block-level circuit design from architecture to tape-out.
• Address analog and mixed-signal challenges across architectures.
• Collaborate with architecture, layout, and verification teams.
• Post-layout verification and silicon validation.

Skills

Analog/mixed-signal design

Tape-out experience

High-speed design

Layout experience

System architecture thinking

Education

MS or PhD in Electrical Engineering

Tools

Cadence

SPICE

Job description

Zenovo is seeking a Senior Engineer to join their silicon team and drive the next generation of chips. You’ll own block‑level circuit design from architecture and simulation through implementation and tape‑out, tackling analog and mixed‑signal challenges across ADCs, PLLs, regulators and high‑speed circuits.

You’ll collaborate with architecture, layout and verification teams in a hands‑on, on‑site environment, with multiple tape‑outs and a path to system‑level impact.