Analog IC Design Engineer

Zenovo; Boston (MA); On-site; USD 150,000 - 210,000; Full time

Job summary

Zenovo is seeking a Senior Engineer to join their silicon team and drive the next generation of chips. You’ll own block‑level circuit design from architecture and simulation through implementation and tape‑out, tackling analog and mixed‑signal challenges across ADCs, PLLs, regulators and high‑speed circuits.

You’ll collaborate with architecture, layout and verification teams in a hands‑on, on‑site environment, with multiple tape‑outs and a path to system‑level impact.

Qualifications

• 6+ years in analog/mixed-signal IC design.
• Multiple tape-outs required.
• Experience with ADCs, PLLs, regulators or high-speed circuits.
• Strong Cadence experience.
• Hands-on layout experience is desirable.
• MS or PhD in Electrical Engineering preferred.

Responsibilities

• Own block-level circuit design from architecture to tape-out.
• Address analog and mixed-signal challenges across architectures.
• Collaborate with architecture, layout, and verification teams.
• Post-layout verification and silicon validation.

Skills

Analog/mixed-signal design

Tape-out experience

High-speed design

Layout experience

System architecture thinking

Education

MS or PhD in Electrical Engineering

Tools

Cadence

SPICE

Job description

You need to be able to work onsite 3 days per week

We’re partnering with an expanding semiconductor company developing a new approach to computing, combining analog, mixed-signal and probabilistic circuits for applications across data centres and edge computing.

They’re growing their silicon team and looking for a Senior Engineer to help develop the next generation of chips. We are looking for some one who is strong at Transistor level design and all the way to system level design.

You'll join a 20 +person team that just taped out their third chip and is now defining the architecture for three upcoming chips. This is a ground-floor opportunity to own major pieces of chip design at a company poised to reshape AI acceleration and edge computing.

The Role

You’ll own block‑level circuit design from architecture and simulation through implementation and tape‑out, working across a variety of challenging analog and mixed‑signal problems.

Your work may include:

• ADCs, PLLs, comparators and oscillators
• Regulators and high‑speed / SerDes circuits
• CMOS analog and mixed‑signal design
• PVT, Monte Carlo, PEX and corner analysis
• Post‑layout simulation and silicon validation
• Working closely with architecture, layout and verification teams

What We’re Looking For

• 6+ years' experience in analog/mixed-signal IC design
• Multiple tape‑out experiences
• Experience with ADCs, PLLs, oscillators, regulators or high‑speed designs
• Strong Cadence experience
• Mixed‑signal experience — not purely analog
• FinFET, 28nm/65nm or other advanced‑node experience is a plus
• Hands‑on layout experience is desirable
• MS or PhD in Electrical Engineering preferred

Why Join?

You’ll be joining while the company is developing multiple new chip designs, giving you the opportunity to work on novel silicon, take real ownership of designs and tackle problems outside the usual circuit‑design playbook.

We cannot offer sponsorship.