Principal Analog/Mixed-Signal IC Architect – Tapeout

Calder Search; Waltham (MA); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Calder Search is seeking an experienced Analog/Mixed-Signal IC Design Engineer (Senior to Principal) for the Greater Boston/Waltham area. The role is hybrid with three days onsite.

You will own circuits from topology through tapeout, including transistor-level design and layout cross-collaboration. Ideal candidates have strong fundamentals in analog/mixed-signal CMOS, multiple tapeouts, and proficiency with Cadence tools.

Qualifications

• Strong fundamentals in analog and mixed-signal CMOS IC design.
• Experience designing ADCs/DACs, PLLs, oscillators/VCOs, SerDes, regulators, references or related blocks.
• Multiple tapeout experiences with exposure to returned silicon.
• Strong understanding of small-signal analysis, feedback, stability, poles/zeros and transistor-level circuit behaviour.
• Experience with Cadence Virtuoso / Spectre or comparable IC design tools.
• PVT, Monte Carlo, PEX and corner-analysis experience.
• Understanding of analog layout, matching and parasitic effects.
• MS or PhD in Electrical Engineering, Microelectronics or a related discipline.

Responsibilities

• Transistor-level CMOS circuit design and simulation.
• Architecture and circuit trade-off analysis.
• Analog and mixed-signal block ownership.
• Schematic through layout, verification and tapeout.
• PVT, Monte Carlo, extracted and post-layout simulation.
• Silicon bring-up, characterization and debugging.
• Working across circuit areas rather than being restricted to one narrow speciality.

Skills

Analog CMOS design

Tapeout experience

Cadence tools

Circuit analysis

Education

MS or PhD in Electrical Engineering/Microelectronics

Tools

Cadence Virtuoso

Spectre

Job description

Calder Search is seeking an experienced Analog/Mixed-Signal IC Design Engineer (Senior to Principal) for the Greater Boston/Waltham area. The role is hybrid with three days onsite.

You will own circuits from topology through tapeout, including transistor-level design and layout cross-collaboration. Ideal candidates have strong fundamentals in analog/mixed-signal CMOS, multiple tapeouts, and proficiency with Cadence tools.