Senior Analog IC Layout Engineer — Tapeout Champion

Elevate-Semiconductor-1; San Diego (CA); On-site; USD 145,000 - 175,000; Full time

Benefits offered by this job

Incentive compensation

Comprehensive benefits

Job summary

Elevate-Semiconductor-1 is seeking a Staff Analog Layout Engineer to take technical ownership of the physical layout and verification of complex analog and mixed-signal ICs for the ATE market, spanning 65nm to 100+V BCD technologies.

You will match, analyze parasitics, and drive layouts through tapeout, collaborating with analog design, digital, and packaging teams to optimize performance and manufacturability.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 8 years of professional experience in analog and mixed-signal IC layout design.
• Strong understanding of analog CMOS circuits and device physics.
• Solid knowledge of IC design, qualification, and manufacturing lifecycle.
• Hands-on experience with industry-standard EDA tools such as Cadence, Mentor Graphics, or Tanner.
• Proficiency in LVS and DRC verification using Cadence or Mentor tools.

Responsibilities

• Perform physical layout of analog and mixed-signal ICs at block and full-chip level.
• Develop floorplans and optimize component placement for area, performance and power.
• Perform LVS and DRC verification to ensure layout accuracy and process compliance.
• Collaborate with design engineers to translate circuit requirements into layouts.
• Partner with digital design, packaging, and cross-functional teams to optimize chip performance.
• Troubleshoot and resolve layout, verification, and manufacturability issues.

Skills

Analog IC layout

LVS/DRC knowledge

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence

Mentor Graphics

Tanner

LVS/DRC verification tools

Job description

Elevate-Semiconductor-1 is seeking a Staff Analog Layout Engineer to take technical ownership of the physical layout and verification of complex analog and mixed-signal ICs for the ATE market, spanning 65nm to 100+V BCD technologies.

You will match, analyze parasitics, and drive layouts through tapeout, collaborating with analog design, digital, and packaging teams to optimize performance and manufacturability.