Senior Analog Design Architect – DRAM & AI-Ready Silicon

Micron Technology, Inc; Boise (ID); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical, dental and vision plans inall

Income protection programs

Paid family leave

Paid holidays

Job summary

Micron Technology, Inc. in Boise, Idaho seeks a Principal Analog Design Engineer to shape next‑gen DRAM circuits, influencing performance and reliability across products. You will collaborate with design, verification and product teams worldwide, mentoring engineers and driving post‑layout validation as silicon ships at scale.

Candidates bring 10+ years in analog/mixed‑signal IC design, strong SPICE/Verilog skills, and a track record mentoring teams in a fast‑paced environment.

Qualifications

• Bachelor’s degree in Electrical Engineering with 10+ years of semiconductor design experience.
• Strong analog circuit design fundamentals with experience in regulators, charge pumps, oscillators, current references, bandgaps, or comparators.
• Proficiency with SPICE and Verilog modeling and simulation.
• Ability to supervise the physical layout of analog circuits.
• Experience working across technical and non‑technical teams.

Responsibilities

• Design, optimize, and verify block‑level analog and mixed‑signal circuits for DRAM
• Propose, evaluate, and implement new or improved circuit topologies to enhance block PPAC
• Work with internal data science and EDA vendors to leverage agentic AI and AI‑assisted design flows for circuit optimization
• Expand verification coverage to strengthen robustness and mass‑production yield
• Partner with global design groups, guide layout through post‑layout simulation, support silicon‑to‑simulation correlation, and operate independently to define solutions and methods

Skills

Analog circuit design

SPICE & Verilog

Layout supervision

Cross-functional teamwork

Education

MSEE

BSEE

Tools

SPICE

Verilog

Job description

Micron Technology, Inc. in Boise, Idaho seeks a Principal Analog Design Engineer to shape next‑gen DRAM circuits, influencing performance and reliability across products. You will collaborate with design, verification and product teams worldwide, mentoring engineers and driving post‑layout validation as silicon ships at scale.

Candidates bring 10+ years in analog/mixed‑signal IC design, strong SPICE/Verilog skills, and a track record mentoring teams in a fast‑paced environment.