Lead Analog Design Engineer - DRAM, AI‑Assisted Circuits

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 160,000 - 210,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Paid holidays

Paid family leave

Benefits guide

Job summary

Micron Technology, Inc. in Boise, Idaho is seeking a Principal Analog Design Engineer to shape the next generation of Micron memory products, bringing circuit designs to life and directly influencing performance, quality and reliability.

You will design, optimize and verify block-level analog and mixed-signal circuits for DRAM, collaborate with global teams, and guide layout through post-layout verification to ensure silicon-to-simulation correlation.

Qualifications

• Bachelor's degree in Electrical Engineering with 10+ years in semiconductor design.
• Strong analog circuit fundamentals (regulators, charge pumps, oscillators, references, band-gaps, comparators).
• Proficiency with SPICE and Verilog modeling/simulation.
• Ability to supervise physical layout of analog circuits.
• Experience working across technical and non-technical teams.

Responsibilities

• Design, optimize, and verify block-level analog and mixed-signal circuits for DRAM.
• Propose, evaluate, and implement new circuit topologies to enhance performance, power, and cost.
• Work with data science teams and AI-assisted design flows for circuit optimization.
• Expand verification coverage to strengthen robustness and yields.
• Partner with global design groups and guide layout through post-layout simulation.

Skills

Analog circuit design

SPICE modeling

Verilog modeling

Cross-functional collaboration

Mentoring engineers

Education

Bachelor's degree in Electrical Engineering

MSEE or BSEE with 12+ years experience

Job description

Micron Technology, Inc. in Boise, Idaho is seeking a Principal Analog Design Engineer to shape the next generation of Micron memory products, bringing circuit designs to life and directly influencing performance, quality and reliability.

You will design, optimize and verify block-level analog and mixed-signal circuits for DRAM, collaborate with global teams, and guide layout through post-layout verification to ensure silicon-to-simulation correlation.