Principal Analog IC Design Engineer — DRAM Innovation

Micron Technology, Inc; Boise (ID); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid time off

Paid holidays

Benefits portal information

Job summary

Micron Technology, Inc. seeks a Principal or MTS in Analog Design to join the DRAM IP Design team in Boise, Idaho.

You will help shape the next generation of memory products, collaborating with global design, verification, and product groups to bring circuits from concept to silicon. You will mentor junior engineers, drive analog blocks, and support layout with post‑layout verification to ensure performance and yield across processes.

Qualifications

• Bachelor’s degree in Electrical Engineering with 12+ years of semiconductor design experience.
• Strong analog circuit fundamentals and experience with regulators, charge pumps, oscillators, bandgaps, or comparators.
• Proficiency with SPICE and Verilog modeling and simulation.
• Ability to supervise physical layout work of analog circuits.
• Experience collaborating with technical and non-technical teams.

Responsibilities

• Design, optimize, and verify analog and mixed‑signal circuits for DRAM projects.
• Collaborate with data science teams and EDA vendors to improve AI‑assisted design flow.
• Propose and implement new circuit topologies to enhance circuit performance.
• Improve design verification scope to increase robustness and yield.
• Mentor junior designers and provide layout guidance through post‑layout simulation.

Skills

Analog circuit design

SPICE modeling

Verilog modeling

Leadership / mentoring

Cross-functional collaboration

Education

Bachelor’s degree in Electrical Engineering

MSEE

BSEE

Job description

Micron Technology, Inc. seeks a Principal or MTS in Analog Design to join the DRAM IP Design team in Boise, Idaho.

You will help shape the next generation of memory products, collaborating with global design, verification, and product groups to bring circuits from concept to silicon. You will mentor junior engineers, drive analog blocks, and support layout with post‑layout verification to ensure performance and yield across processes.