RTL Design Engineer — AI-Driven Silicon Architect

Energy Jobline ZR; Palo Alto (CA); In loco; USD 140.000 - 240.000; Tempo pieno

Descrizione del lavoro

Voltai is developing world models and agents to learn, evaluate, plan, experiment, and interact with the physical world. The role focuses on designing and owning RTL for production silicon, from microarchitecture to signoff-ready code, collaborating with customers and verification teams.

You will work on real chip programs with leading semiconductor companies, driving designs through lint, CDC, and timing closure, and reviewing AI-generated RTL to define high-quality design standards.

Competenze

• 5+ years of RTL design experience on chips that taped out.
• Expert SystemVerilog/Verilog and strong microarchitecture skills.
• Hands-on experience with lint, CDC, synthesis, and timing-aware design.
• Familiarity with common protocols (AXI, PCIe, Ethernet, DDR, or similar).
• Python or Tcl scripting.

Mansioni

• Own microarchitecture and RTL implementation for IP blocks and subsystems in SystemVerilog.
• Drive designs through lint, CDC/RDC, synthesis, and timing closure with the backend team.
• Partner with verification and formal teams on test plans, assertions, and coverage closure.
• Debug complex functional and timing issues across simulation, emulation, and silicon.
• Review and evaluate AI-generated RTL, and help define what correct, high-quality design looks like.
• Work directly with customer design teams when needed.

Conoscenze

RTL design expertise

SystemVerilog/Verilog

Lint/CDC/Synthesis

Timing closure

Common protocols (AXI PCIe EthernetDDR

Python or Tcl scripting

Descrizione del lavoro

Voltai is developing world models and agents to learn, evaluate, plan, experiment, and interact with the physical world. The role focuses on designing and owning RTL for production silicon, from microarchitecture to signoff-ready code, collaborating with customers and verification teams.

You will work on real chip programs with leading semiconductor companies, driving designs through lint, CDC, and timing closure, and reviewing AI-generated RTL to define high-quality design standards.