Formal Verification and RTL Design Software Engineer

Astera Labs; San Jose (CA); On-site; USD 161,000 - 200,000; Full time

Job summary

Astera Labs in San Jose is seeking a Senior Software Engineer for AI-enabled RTL design and formal verification. You will build and deploy AI-driven agents to accelerate RTL and physical design, static analysis, and verification workflows.

You will develop agentic AI solutions, integrate them with CAD/EDA flows, and create design databases and dashboards to surface engineering data for faster design closure. Collaboration with RTL, DV, and CAD/EDA teams is essential.

Qualifications

• Bachelor's or master's in EE/CS or equivalent experience.
• 4–10 years of software engineering with RTL/verification exposure.
• Proficiency in Python for rapid prototyping.
• Experience with LLMs and multi-agent systems.
• Familiarity with Verilog/SystemVerilog and formal verification tools.

Responsibilities

• Design and deploy AI apps using LLMs and agentic frameworks for RTL/verification.
• Build infra to deploy AI assistants and multi-turn dialogues for designers and engineers.
• Develop agentic AI solutions for RTL linting, RTL optimization, bug triage, formal proof convergence.
• Integrate solutions with CAD/EDA flows.
• Create design databases and dashboards to surface engineering data.
• Collaborate with RTL, DV, formal verification, and CAD/EDA teams.

Skills

Python

RTL design

Formal verification

LLMs / AI for CAD

Data structures & algorithms

Communication skills

Education

Bachelor's or Master's in EE/CS

Tools

Verilog/SystemVerilog

JasperGold / VC Formal

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Senior Software Engineer – AI for RTL Design & Formal Verification

Join Astera Labs' AppliedAI organization, where we're building the connectivity infrastructure that powers AI and cloud data centers. Our team sits at the intersection of digital and analog design, verification, and AI tooling, tackling the complexity of next-generation semiconductor products at the pace our industry demands. We're looking to develop and deploy AI-driven agents that accelerate RTL and physical design, static analysis, and formal verification workflows. The ideal candidate combines a strong ASIC and software engineering background with hands-on exposure to digital or analog design or verification, and is excited to apply LLMs and agentic systems to real chip design problems.

What You'll Be Doing

Design, develop, and deploy AI applications using LLMs, agentic frameworks, and related technologies to support RTL, physical and analog design, static/lint checking, and formal verification flows. Build infrastructure to deploy LLM-powered engineering assistants and multi-turn dialogue systems that help designers and verification engineers debug faster and close coverage sooner. Develop agentic AI solutions for tasks such as RTL rule and lint checking, RTL optimization, bug triage, formal proof convergence, and static verification report analysis; fine-tune and integrate these solutions with existing CAD/EDA flows. Build and maintain design databases and dashboards that combine agentic and deterministic retrieval to surface relevant engineering data and speed up design closure. Collaborate closely with RTL design, DV, formal verification, and CAD/EDA teams to understand pain points and translate them into AI-assisted tooling.

Basic Qualifications

• Bachelor's, Master's degree in Electrical Engineering, Computer Science/Engineering, or equivalent experience.
• 4-10 years of industry experience in software engineering, with direct exposure to RTL design, static/lint verification, or formal verification methodologies.
• Proficiency in Python for rapid prototyping, with strong fundamentals in data structures, algorithms, and software engineering practices.
• Experience with LLMs, including fine-tuning, building multi-agent systems, RAG pipelines, and vector databases.
• Familiarity with RTL design languages (Verilog/SystemVerilog) and formal/static verification tools (e.g., JasperGold, VC Formal, or similar) is strongly preferred.
• Strong analytical, communication, and interpersonal skills, with a proven ability to work effectively in a fast-paced, cross-functional startup environment.
• A proactive, self-directed approach to problem-solving and comfort operating with ambiguity.

Ways to Stand Out

• Direct experience applying AI/ML techniques to EDA or CAD flow problems.
• Proficiency in modern software engineering practices, including version control, testing, and CI/CD.
• Experience with formal property verification, assertion-based verification (SVA), or static timing/lint tools.
• A track record of learning across disparate domains (AI/ML and hardware design) and combining them into novel engineering solutions.

Salary range is $160,500 to $200,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.